The present invention relates generally to the instruction processing unit or instruction fetching and execution portion of a digital computer system. More particularly, the invention relates to an apparatus and method for handling interrupts in a so-called "pipelined" instruction processor.
Computer architectures generally require most interruptions to the stream of instruction execution to be associated with a particular instruction. The degree to which this requirement is fulfilled is called "precision" i.e., an interrupting condition "i" is precise if it can be positively associated with the execution of instruction "n".
In a non-pipelined processor--that is, a processor where one instruction is executed in its entirety before another is started - precision in interrupt reporting is readily achieved since at any given time there is only one instruction with which an interrupt could be associated. However, reporting interrupts precisely in a pipelined processor is much more difficult since many instructions may be in various stages of execution simultaneously. Thus, upon the occurrence of an interrupting condition i, it may not be clear with which of the currently executing instructions - n, n+1, n+2, and so on--to associate with the interrupt. Furthermore, multiple interrupts may occur substantially simultaneously, creating the question of which of these to report and handle first. Often, the system architecture dictates that only the oldest and highest priority interrupt may be reported.
The difficulty of precisely reporting interrupts in a pipelined processor has been faced by designers in the past. Some, in fact, have circumvented the problem by deviating from the system architecture and reporting interrupts imprecisely. See, for example, D. W. Anderson, et al., "The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling,", IBM Journal, January, 1967. Thus, in a stream of executing instructions n, n+1, n+2, and so on, that is interrupted by condition i, the interrupt cannot be accurately associated with any of the currently executing instructions.
In a computing environment where interrupts are quite infrequent, it is perhaps permissible to report interrupts imprecisely. However, with the advent of virtual memory, precise interrupt reporting and handling has become mandatory because interrupts caused by the virtual memory management process must be associated with the instruction that caused them. In particular, "address translation lookaside buffer" (or "TLB") miss interrupts are caused when the translation lookaside buffer does not produce the absolute memory address associated with the virtual memory address contained in an instruction. Such "TLB misses"-meaning, the absolute address is missing from the translation lookaside buffer--occur at a comparatively high frequency and are often resolved by performing an address translation and then re-executing part or all of the instruction that caused the TLB miss. In order to re-execute the instruction, it is necessary to determine exactly (precisely) which instruction caused the TLB miss. Also, because they occur more frequently than other interrupts, the speed with which TLB misses are reported and handled can impact processor performance significantly.
The problem of precise interrupt reporting is further exacerbated when additional functional units extend the main instruction-fetch and execution (I/E) unit pipeline. Such functional units might include an instruction and data storage unit, a floating-point execution unit, a vector execution unit, and so on, and are driven by the same instruction stream as the I/E unit. In particular, the I/E unit fetches instructions from the storage unit and forwards instructions or commands to the functional units for execution as required while continuing to execute additional instructions in the stream for as long as possible, perhaps until some result to be produced by a functional unit is required for further computation. Thus it can be seen that a large number of instructions may be in various phases of execution concurrently across the system and, consequently, interrupts may occur simultaneously in any or all of the units, making precise interrupt reporting a formidable problem indeed.
A number of schemes for precisely reporting interrupts in a pipelined processing system with multiple functional units have been implemented or proposed. The IBM 3090.TM. vector facility uses an interrupt pipeline with a complex hardware structure that is difficult to design and control. See S. G. Tucker, "The IBM 3090 System: An Overview,", IBM System Journal, Vol. 25, No. 1, 1986. Smith and Pleszkun propose other elaborate hardware structures--reorder buffers, history buffers, future files, etc.-- which have yet to be proven viable. See J. E. Smith and A. R. Pleszkun "Implementation of Precise Interrupts in Pipelined Processors," Proc. 12th Annual International Symposium on Computer Architecture, pp. 36-44, June 1985.